摘要
本研究針對數位系統設計教學，提出一低成本的數位電路測試框架，以協助學生有效地掌握電路設計和測試技巧，同時解決昂貴測試設備需求和專業培訓的挑戰。本研究的兩項主要工作，首先將測試框架和測試電路，燒錄至同一個可程式系統晶片（PSoC）中，減少對外部測試設備的依賴。其次使用常見的數位系統設計方法，在真實的教學環境中評估測試框架的實際可用性。這些工作項目已在PYNQ-Z2平台上完成實際測試，處理器端的程式設計採用了Python，而數位系統的雛形和測試框架則使用Verilog完成電路描述，最後透過Xilinx Vivado進行了高階合成。測試框架使用EMIO和四相通訊協定，實現了寫入測試資料、執行測試、讀取結果和完成測試的連續處理流程。在實際測試中，選擇了乘法器、計數器狀態機，以及4位元SPI通訊模組作為驗證電路，以確保測試框架的驗證功能。透過實驗，成功處理了與時脈相關的錯誤偵測，驗證了測試框架的精確狀態轉變識別能力，並展示了其在除錯數位I/O通訊方面的功能。本研究成功建立了基於PSoC Zynq 7000系列開發板的數位系統測試框架，減少對外部訊號產生與量測設備的依賴，提供一個低成本的數位系統測試平台，以滿足各種數位電路教學和設計的需求。
關鍵詞：數位系統、電路設計、電路測試、可程式系統晶片、四相通訊
Abstract
This research centers on educating students in digital system design and introduces a low-cost digital testing framework. A user-friendly and accessible testing framework based on PSoC Zynq 7000 series development board is developed. Our aim is to support students in mastering circuit design and testing skills efficiently, eliminating the obstacles associated with costly equipment demands and specialized training. The study targets two primary objectives. Firstly, both the testing framework and the circuits under test are incorporated into the same PSoC chip, aiming to minimize reliance on expensive external devices. Secondly, common digital system design methods are used to evaluate the practical viability of the testing framework within real-world digital system design education contexts. These work tasks have been subjected to practical testing on the PYNQ-Z2 platform. The program design on the processor side utilizes Python, while the digital system's prototype and testing framework are constructed using Verilog for circuit description. Ultimately, the high-level synthesis is conducted through Xilinx Vivado. The testing framework incorporates EMIO and a quadrature communication protocol, enabling a continuous processing flow encompassing test data writing, test execution, result reading, and test completion. During practical testing, a multiplier, a counter state machine, and a 4-bit SPI communication module are selected as validation circuits to ensure the verification function of the testing framework. Through experimentation, clock-related error detection is effectively handled, the testing framework’s ability to identify precise state change is validated, and its exceptional performance in debugging digital I/O communication is demonstrated. This study has successfully established a digital system testing framework using the PSoC Zynq 7000 series development board. This reduces the reliance for external signal generating and measuring equipment, resulting in a cost-efficient educational platform. This platform caters to a range of digital circuit education and design needs.
Keywords: Digital systems, Circuit design, Circuit testing, PSoC, 4-phase protocol