摘要
本論文提出一雛型化非同步電路(asynchronous circuits)及測試的新方法，該方法適用於初期設計想法探索及非同步電路設計教學。非同步VLSI的設計方法已發展多年且日趨成熟，學界及業界亦提供大量EDA工具，但對大多數位系統設計工程師而言，非同步電路設計仍是相當陌生的課題。造成此窘境的原因可歸納為以下兩點，在一般大專院校的數位系統設計課程，非同步電路雖然屬於進階課程，但常被視為非主流的數位系統設計，因此授課教師通常會略過此章節。此外，目前缺乏成熟的非同步電路實現技術及合成工具，無法如同步數位系統般可使用FPGAs快速雛型電路實現及實作驗證平台。就當前主流VLSI技術發展趨勢而論，短期內非同步電路應無機會取代同步電路(synchronous circuits)。但團隊始終相信，非同步設計將有助於解決同步電路設計上所遭遇的技術困境。因此重整先前所開發的基於FPGAs非同步電路實現技術，改用可程式化系統晶片(SoPC)來實現非同步電路及測試輔助系統，此一改良非同步系統實現方法，可降低測試輔助系統對待測電路(CUT)的干擾，並使測試向量的產生及供給更具彈性。以下以簡單的電路實驗來分析本文所提的新創方法，評估結果證明足以應付大部份非同步電路雛型及測試需求，而該方法亦可作非同步系統設計教學之快速雛型及電路驗證平台。
關鍵詞：非同步、硬體描述語言、可程式化系統晶片、交握、微處理器
Abstract
We proposed a novel approach of using SoPC to prototype asynchronous circuits with on-board diagnostics testing. The method can be used in the early design stage of exploring asynchronous systems, and it is also an affordable experimenting platform for teaching asynchronous circuits. Asynchronous VLSI design methods have been developed for years. Some open-source asynchronous EDA tools for logic-level synthesis are obtainable freely from the internet. However, asynchronous circuits are still mysterious for most of the circuit design engineers. The cause of this dilemma can be summarized as the following two reasons. In today’s college course, the chapter of the asynchronous circuits is rarely taught or mentioned. Asynchronous VLSI is usually classified as an advanced topic and skipped by most teachers of the digital design classes. Also, lack of mature circuit-level synthesis tools, implementing asynchronous systems require much more design efforts than building synchronous counterparts. Judging from the near future trend of VLSI technology, there is not much chance that asynchronous circuits will become as popular as synchronous circuits. However, we believe asynchronous design can help to solve some serious challenges commonly seem in today’s synchronous systems. Therefore, we proposed a simple method of using a low-end SoPC platform to prototype asynchronous circuits. In this thesis, we layout the proposed method in detail with some sample designs. Although, we still not able to perform a state-level and real-time asynchronous verification for the test subjects. All the sample designs were passed by a series of high speed on-board functional tests. Based on the experimenting result, we have faith in the usefulness of the proposed method.