摘要
本研究實現了一個低成本高速度的電流汲取式數位類比轉換器電路；在架構層次，使用隨機溫度計式編碼，提供了連續選擇、隨機與較少元件切換動作的特性，因而大幅度降低了元件不匹配所造成的諧波失真問題；在電路層次，使用歸零電路，在不影響操作速度的前提下，將輸出節點與控制訊號做了適當的隔離；在佈局層次，提出了創新的混合型佈局方法，針對碗型與線性型兩類最常發生的系統性不匹配進行補償。使用上述三大技術，在1P6M 0.18μm 1.8V CMOS製程下實現了一個12位元、100MHz電流汲取式數位類比轉換器。在100MHz取樣頻率下，無突波動態範圍的量測值均大於75dB。量測結果顯示，使用隨機溫度計式編碼技術，提升了11dB以上的無突波動態範圍；使用歸零電路，可以在1/2取樣頻率輸入時，避免10dB的無突波動態範圍衰退。本研究實現的數位類比轉換器，主動面積小於0.12mm2，擁有低成本的特性。
關鍵詞：數位類比轉換器、隨機、歸零、佈局方法
Abstract
The design of a low-cost high-speed current-steering digital-to-analog converter (DAC) is presented. On the architecture level, the randomized thermometer-coding (RTC), which offers consecutive selection, randomization, and less element switching activity, is used. Therefore, harmonic distortion caused by element mismatches can be significantly suppressed. On the circuit level, a return-to-zero (RTZ) circuit, which can isolate the DAC output nodes from the coupling of the control signals without sacrificing speed, is adopted. On the layout level, a novel hybrid layout scheme is proposed. This scheme can compromise the quadratic and linear error distribution of systematic element-mismatch. Using the above three techniques, a 12-bit 100-MHz current-steering DAC is implemented in a 1P6M 0.18-μm 1.8-V CMOS process. The measured spurious-free dynamic range (SFDR) is higher than 75dB at a 100MHz sampling frequency. The measurement results show that the RTC technique improves the SFDR by more than 11dB and the RTZ circuit prevents a 10dB SFDR drop when the input signal frequency is close to half the sampling frequency. The low-cost DAC has an active area of less than 0.12-mm2.
Keywords: Digital-to-analog Converter, Randomization, Return-to-zero, Layout Scheme